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GS81302S08/09/18/36E-375/350/333/300/250
165-Bump BGA Commercial Temp Industrial Temp
144Mb SigmaSIOTM DDR -II Burst of 2 SRAM
375 MHz–250 MHz 1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future
frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available
SigmaSIO™ Family Overview
GS81302S08/09/18/36 are built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the
Bottom View
165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO DDR-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data’s destination.
Each internal read and write operation in a SigmaSIO DDR-II B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore, the address field of a SigmaSIO DDR-II B2 is always one address pin less than the advertised index depth (e.g., the 16M x 8 has an 8M addressable index).
Parameter Synopsis
tKHKH tKHQV
-375 2.66 ns 0.45 ns
-350 2.86 ns 0.45 ns
-333 3.0 ns 0.45 ns
-300 3.3 ns 0.45 ns
-250 4.0 ns 0.45 ns
Rev: 1.03b 12/2011
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS81302S08/09/18/36E-375/350/333/300/250
16M x 8 SigmaQuad SRAM—Top View
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A CQ SA SA R/W NW1 K SA LD SA
B
NC
NC
NC
SA
NC/SA (288Mb)
K
NW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC D4 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D5
Q5
VDDQ
VDD
VSS
VDD VDDQ NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D7 NC VSS SA SA SA VSS NC
P NC NC Q7 SA SA C SA SA NC
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. B5 is the expansion address.
10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
Rev: 1.03b 12/2011
2/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS81302S08/09/18/36E-375/350/333/300/250
16M x 9 SigmaQuad SRAM—Top View
123456789
A CQ SA SA R/W NC K SA LD SA
B
NC
NC
NC
SA
NC/SA (288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC D5 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D6
Q6
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D8 NC VSS SA SA SA VSS NC
P NC NC Q8 SA SA C SA SA NC
R TDO TCK
Notes: 1. BW0 controls writes to D0:D7. 2. B5 is the expansion address.
SA SA SA C SA SA SA 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
10 SA NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS
11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI
Rev: 1.03b 12/2011
3/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
GS81302S08/09/.