144Mb SigmaQuad-IIIe Burst of 2 ECCRAM
GS81313LQ18/36GK-800/714/600
260-Pin BGA Com & Ind Temp HSTL I/O
144Mb SigmaQuad-IIIe™ Burst of 2 ECCRAM™
Up to 800 M...
Description
GS81313LQ18/36GK-800/714/600
260-Pin BGA Com & Ind Temp HSTL I/O
144Mb SigmaQuad-IIIe™ Burst of 2 ECCRAM™
Up to 800 MHz 1.25V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ
Features
4Mb x 36 and 8Mb x 18 organizations available 800 MHz maximum operating frequency 1.6 BT/s peak transaction rate (in billions per second) 115 Gb/s peak data bandwidth (in x36 devices) Separate I/O DDR Data Buses Non-multiplexed DDR Address Bus Two operations - Read and Write - per clock cycle Burst of 2 Read and Write operations 3 cycle Read Latency On-chip ECC with virtually zero SER 1.25V ~ 1.3V core voltage 1.2V ~ 1.3V HSTL I/O interface Configurable ODT (on-die termination) ZQ pin for programmable driver impedance ZT pin for programmable ODT impedance IEEE 1149.1 JTAG-compliant Boundary Scan 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance ECCRAMs. Although very similar to GSI's second generation of networking SRAMs (the SigmaQuad-II/SigmaDDR-II family), these third generation devices offer several new features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81313LQ18/36GK SigmaQuad-IIIe ECCRAMs are synchronous devices. They employ three pairs of positive and negative input clocks; one pair of master clocks, CK and CK, and two pairs of write data clocks, KD[1:0] and K...
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