GS81314LQ18GK

GS81314LQ18/36GK-133/120/106 260-Pin BGA Com & Ind Temp HSTL I/O 144Mb SigmaQuad-IVe™ Burst of 2 Multi-Bank ECCRAM™ Up to 1333 MHz 1.25V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ Features 4Mb x 36 and 8Mb x 18 organizations available Organized as 16 logical memory banks 1333 MHz maximum operating frequency 2.666 BT/s peak transaction rate (in billions per second) 192 Gb/s peak data bandwidth (in x36 devices) Separate I/O DDR Data Buses Non-multiplexed DDR Address Bus Two operations - Read and Write - per clock cycle Certain address/bank restrictions on Read and Write ops Burst of 2 Read and Write operations 6 cycle Read Latency On-chip ECC with virtually zero SER Loopback signal timing training capability 1.25V ~ 1.3V nominal core voltage 1.2V ~ 1.3V HSTL I/O interface Configuration registers Configurable ODT (on-die termination) ZQ pin for programmable driver impedance ZT pin for programmable ODT impedance IEEE 1149.1 JTAG-compliant Boundary Scan 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- compliant BGA package SigmaQuad-IVe™ Family Overview SigmaQuad-IVe ECCRAMs are the Separate I/O half of the SigmaQuad-IVe/SigmaDDR-IVe family of high performance ECCRAMs. Although similar to GSI's third generation of networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe family), these fourth generation devices offer several new features that help enable significantly higher performance. Clocking and Addressing Schemes The GS81314LQ18/36GK SigmaQuad-IVe...