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GS81314LQ36GK Dataheets PDF



Part Number GS81314LQ36GK
Manufacturers GSI Technology
Logo GSI Technology
Description 144Mb SigmaQuad-IVe Burst of 2 Multi-Bank ECCRAM
Datasheet GS81314LQ36GK DatasheetGS81314LQ36GK Datasheet (PDF)

GS81314LQ18/36GK-133/120/106 260-Pin BGA Com & Ind Temp HSTL I/O 144Mb SigmaQuad-IVe™ Burst of 2 Multi-Bank ECCRAM™ Up to 1333 MHz 1.25V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ Features • 4Mb x 36 and 8Mb x 18 organizations available • Organized as 16 logical memory banks • 1333 MHz maximum operating frequency • 2.666 BT/s peak transaction rate (in billions per second) • 192 Gb/s peak data bandwidth (in x36 devices) • Separate I/O DDR Data Buses • Non-multiplexed DDR Address Bus • Two operations - Read .

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GS81314LQ18/36GK-133/120/106 260-Pin BGA Com & Ind Temp HSTL I/O 144Mb SigmaQuad-IVe™ Burst of 2 Multi-Bank ECCRAM™ Up to 1333 MHz 1.25V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ Features • 4Mb x 36 and 8Mb x 18 organizations available • Organized as 16 logical memory banks • 1333 MHz maximum operating frequency • 2.666 BT/s peak transaction rate (in billions per second) • 192 Gb/s peak data bandwidth (in x36 devices) • Separate I/O DDR Data Buses • Non-multiplexed DDR Address Bus • Two operations - Read and Write - per clock cycle • Certain address/bank restrictions on Read and Write ops • Burst of 2 Read and Write operations • 6 cycle Read Latency • On-chip ECC with virtually zero SER • Loopback signal timing training capability • 1.25V ~ 1.3V nominal core voltage • 1.2V ~ 1.3V HSTL I/O interface • Configuration registers • Configurable ODT (on-die termination) • ZQ pin for programmable driver impedance • ZT pin for programmable ODT impedance • IEEE 1149.1 JTAG-compliant Boundary Scan • 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- compliant BGA package SigmaQuad-IVe™ Family Overview SigmaQuad-IVe ECCRAMs are the Separate I/O half of the SigmaQuad-IVe/SigmaDDR-IVe family of high performance ECCRAMs. Although similar to GSI's third generation of networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe family), these fourth generation devices offer several new features that help enable significantly higher performance. Clocking and Addressing Schemes The GS81314LQ18/36GK SigmaQuad-IVe ECCRAMs are synchronous devices. They employ three pairs of positive and negative input clocks; one pair of master clocks, CK and CK, and two pairs of write data clocks, KD[1:0] and KD[1:0]. All six input clocks are single-ended; that is, each is received by a dedicated input buffer. CK and CK are used to latch address and control inputs, and to control all output timing. KD[1:0] and KD[1:0] are used solely to latch data inputs. Each internal read and write operation in a SigmaQuad-IVe B2 ECCRAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore, the address field of a SigmaQuad-IVe B2 ECCRAM is always one address pin less than the advertised index depth (e.g. the 8M x 18 has 4M addressable index). On-Chip Error Correction Code GSI's ECCRAMs implement an ECC algorithm that detects and corrects all single-bit memory errors, including those induced by SER events such as cosmic rays, alpha particles, etc. The resulting Soft Error Rate of these devices is anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude improvement over comparable SRAMs with no on-chip ECC, which typically have an SER of 200 FITs/Mb or more. All quoted SER values are at sea level in New York City. Speed Grade -133 -120 -106 Parameter Synopsis Max Operating Frequency 1333 MHz 1200 MHz 1066 MHz Read Latency 6 cycles 6 cycles 6 cycles VDD 1.2V to 1.35V 1.2V to 1.35V 1.2V to 1.35V Rev: 1.09 5/2016 1/40 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2014, GSI Technology GS81314LQ18/36GK-133/120/106 8M x 18 Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VDD VDDQ VDD VDDQ NC (RSVD) MCH (CFG) MRW ZQ PZT1 VDDQ VDD VDDQ VDD B VSS NUO VSS NUI MCL MCL (B4M) NC (RSVD) MCH (SIOM) PZT0 D0 VSS Q0 VSS C Q17 VDDQ D17 VDDQ VSS SA13 VDD SA14 VSS VDDQ NUI VDDQ NUO D VSS NUO VSS NUI SA19 VDDQ NC (288 Mb) VDDQ SA20 D1 VSS Q1 VSS E Q16 VDDQ D16 VDD VSS SA11 VSS SA12 VSS VDD NUI VDDQ NUO F VSS NUO VSS NUI SA17 VDD VDDQ VDD SA18 D2 VSS Q2 VSS G Q15 NUO D15 NUI VSS SA9 MZT1 SA10 VSS D3 NUI Q3 NUO H Q14 VDDQ D14 VDDQ SA15 VDDQ W VDDQ SA16 VDDQ NUI VDDQ NUO J VSS NUO VSS NUI VSS SA7 VSS SA8 VSS D4 VSS Q4 VSS K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0 L CQ1 VSS QVLD1 Vss KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0 M VSS Q13 VSS D13 VSS SA5 VSS SA6 VSS NUI VSS NUO VSS N NUO VDDQ NUI VDDQ PLL VDDQ R VDDQ MCL VDDQ D5 VDDQ Q5 P NUO Q12 NUI D12 VSS SA3 MZT0 SA4 VSS NUI D6 NUO Q6 R VSS Q11 VSS D11 MCH VDD VDDQ VDD RST NUI VSS NUO VSS T NUO VDDQ NUI VDD VSS SA1 VSS SA2 VSS VDD D7 VDDQ Q7 U VSS Q10 VSS D10 NC (576 Mb) VDDQ NC (RSVD) VDDQ NC (1152 Mb) NUI VSS NUO VSS V NUO VDDQ NUI VDDQ VSS SA21 (x18) VDD SA0 (B2) VSS VDDQ D8 VDDQ Q8 W VSS Q9 VSS D9 TCK MCL RCS MCL TMS NUI VSS NUO VSS Y VDD VDDQ VDD VDDQ TDO ZT NC (RSVD) MCL TDI VDDQ VDD VDDQ VDD Notes: 1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device. 2. Pin 5R must be tied High in this device. 3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration. 4. Pin 6B is defined as mode pin B4M in the pinout standard. It mus.


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