GS8180QV36BGD

GS8180QV18/36BD-200/167 165-Bump BGA Commercial Temp Industrial Temp 18Mb Burst of 2 SigmaQuad SRAM 200 MHz–167 MHz 2.5 V VDD 1.8 V or 1.5 V I/O Features Simultaneous Read and Write SigmaQuad™ Interface JEDEC-standard pinout and package Dual DoubleData Rate interface Byte Write controls sampled at data-in time Burst of 2 Read and Write 2.5 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ mode pin for programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan Pin-compatible with future 36Mb, 72Mb, and 144Mb devices RoHS-compliant 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package SigmaRAM™ Family Overview GS8180QV18/36B are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand. Clocking and Addressing Schemes A Burst of 2 SigmaQuad SRAM is a synchronous device. It employs two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to ma...