GS82582DT39GE

165-Bump BGA Commercial Temp Industrial Temp GS82582DT21/39GE-675S/633S/550S 288Mb SigmaQuad-II+ Burst of 4 SRAM Up to 675 MHz 1.8 V VDD 1.5 V I/O Features For use with GSI FPGA-based Controller IP 3.0 Clock Latency Simultaneous Read and Write SigmaQuad™ Interface JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time Burst of 4 Read and Write Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs 1.8 V +100/–100 mV core power supply 1.5 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ pin for programmable output drive strength Data Valid Pin (QVLD) Support IEEE 1149.1 JTAG-compliant Boundary Scan 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package 6/6 RoHS-compliant 165-bump BGA package SigmaQuad™ Family Overview The GS82582DT21/39GE are built in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 301,989,888-bit (288Mb) SRAMs. The GS82582DT21/39GE SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS82582DT21/39GE SigmaQuad-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a ...