GS82583EQ36GK

GS82583EQ18/36GK-500/450/400 260-Pin BGA Commercial Temp Industrial Temp 288Mb SigmaQuad-IIIe™ Burst of 2 SRAM Up to 500 MHz 1.3V VDD 1.2V, 1.3V, or 1.5V VDDQ Features 8Mb x 36 and 16Mb x 18 organizations available 500 MHz maximum operating frequency 1.0 BT/s peak transaction rate (in billions per second) 72 Gb/s peak data bandwidth (in x36 devices) Separate I/O DDR Data Buses Non-multiplexed DDR Address Bus Two operations - Read and Write - per clock cycle Burst of 2 Read and Write operations 3 cycle Read Latency 1.3V nominal core voltage 1.2V, 1.3V, or 1.5V HSTL I/O interface Configurable ODT (on-die termination) ZQ pin for programmable driver impedance ZT pin for programmable ODT impedance IEEE 1149.1 JTAG-compliant Boundary Scan 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS- compliant BGA package SigmaQuad-IIIe™ Family Overview SigmaQuad-IIIe SRAMs are the Separate I/O half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance SRAMs. Although very similar to GSI's second generation of networking SRAMs (the SigmaQuad-II/SigmaDDR-II family), these third generation devices offer several new features that help enable significantly higher performance. Clocking and Addressing Schemes The GS82583EQ18/36GK SigmaQuad-IIIe SRAMs are synchronous devices. They employ three pairs of positive and negative input clocks; one pair of master clocks, CK and CK, and two pairs of write data clocks, KD[1:0] and KD[1:0]. All six input clocks ar...