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GS8662QT37BGD Dataheets PDF



Part Number GS8662QT37BGD
Manufacturers GSI Technology
Logo GSI Technology
Description 72Mb SigmaQuad-II+ Burst of 2 SRAM
Datasheet GS8662QT37BGD DatasheetGS8662QT37BGD Datasheet (PDF)

GS8662QT07/10/19/37BD-357/333/300/250/200 165-Bump BGA Commercial Temp Industrial Temp 72Mb SigmaQuad-II+TM Burst of 2 SRAM 357 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • Burst of 2 Read and Write • 1.8 V +1.

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GS8662QT07/10/19/37BD-357/333/300/250/200 165-Bump BGA Commercial Temp Industrial Temp 72Mb SigmaQuad-II+TM Burst of 2 SRAM 357 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available SigmaQuad™ Family Overview The GS8662QT07/10/19/37BD are built in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662QT07/10/19/37BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8662QT07/10/19/37BD SigmaQuad-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. Each internal read and write operation in a SigmaQuad-II+ B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II+ B2 RAM is always one address pin less than the advertised index depth (e.g., the 8M x 8 has an 4M addressable index). Parameter Synopsis tKHKH tKHQV -357 2.8 ns 0.45 ns -333 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns Rev: 1.00a 11/2011 1/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8662QT07/10/19/37BD-357/333/300/250/200 8M x 8 SigmaQuad-II SRAM—Top View 123456789 A CQ SA SA W NW1 K NC/SA (144Mb) R SA B NC NC NC SA NC/SA (288Mb) K NW0 SA NC C NC NC NC VSS SA SA SA VSS NC D NC D4 NC VSS VSS VSS VSS VSS NC E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC F NC NC NC VDDQ VDD VSS VDD VDDQ NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC K NC NC NC VDDQ VDD VSS VDD VDDQ NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC M NC NC NC VSS VS.


GS8662QT37BD GS8662QT37BGD GS8672D19BE


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