GS8182D18D

Preliminary GS8182D18D-250/200/167 165-Bump BGA Commercial Temp Industrial Temp 18Mb Burst of 4 SigmaQuad-II SRAM 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Simultaneous Read and Write SigmaQuad™ Interface JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time Burst of 4 Read and Write 1.8 V +150/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ mode pin for programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package Pin-compatible with future 36Mb, 72Mb, and 144Mb devices SigmaRAM™ Family Overview GS8182D18 are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAM...