GS8182Q18D Datasheet (data sheet) PDF





GS8182Q18D Datasheet, 18Mb Burst of 2 SigmaQuad-II SRAM

GS8182Q18D   GS8182Q18D  

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Preliminary GS8182Q18D-200/167/133 165- Bump BGA Commercial Temp Industrial Tem p 18Mb Burst of 2 SigmaQuad-II SRAM 2 00MHz–133MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read a nd Write SigmaQuad™ Interface • JED EC-standard pinout and package • Dual Double Data Rate interface • Byte Wr ite controls sampled at data-in time Burst of 2 Read and Write • 1.8 V + 150/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipeline d read operation • Fully coherent rea d and write pipelines • ZQ mode pin f or programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA p

GS8182Q18D Datasheet, 18Mb Burst of 2 SigmaQuad-II SRAM

GS8182Q18D   GS8182Q18D  
ackage • Pin-compatible with future 36 Mb, 72Mb, and 144Mb devices SigmaRAM™ Family Overview GS8182Q18 are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchr onous SRAMs. They are 18,874,368-bit (1 8Mb) SRAMs. These are the first in a fa mily of wide, very low voltage HSTL I/O SRAMs








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