Document
GS8182T08/09/18/36BD-400/375/333/300/250/200/167
165-Bump BGA Commercial Temp Industrial Temp
18Mb SigmaDDR-II™ Burst of 2 SRAM
400 MHz–167 MHz 1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available
SigmaDDR-II™ Family Overview
The GS8182T08/09/18/36BD are built in compliance with the SigmaDDR-II SRAM pinout stand.