GS82582S36GE

GS82582S18/36GE-400/375/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 288Mb SigmaSIOTM DDR-II Burst of 2 SRAM 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Simultaneous Read and Write SigmaSIO™ Interface JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time DLL circuitry for wide output data valid window and future frequency scaling Burst of 2 Read and Write 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ mode pin for programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan RoHS-compliant 165-bump BGA package SigmaSIO™ Family Overview GS82582S18/36GE are built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 301,989,888-bit (288Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 2SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of...