GS82582T38GE

GS82582T20/38GE-550/500/450/400 165-Bump BGA Commercial Temp Industrial Temp 288Mb SigmaDDR-II+TM Burst of 2 SRAM 550 MHz–400 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features 2.5 Clock Latency Simultaneous Read and Write SigmaDDRTM Interface JEDEC-standard pinout and package Double Data Rate interface Byte Write controls sampled at data-in time Burst of 2 Read and Write On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ pin for programmable output drive strength Data Valid Pin (QVLD) Support IEEE 1149.1 JTAG-compliant Boundary Scan RoHS-compliant 165-bump BGA package SigmaDDR-II™ Family Overview The GS82582T20/38GE are built in compliance with the SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous SRAMs. They are 301,989,888-bit (288Mb) SRAMs. The GS82582T20/38GE SigmaDDR-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS82582T20/38GE SigmaDDR-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. Each internal read and write operation in a SigmaDDR-II+ B2 ...