GS8342S36BD

GS8342S08/09/18/36BD-400/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 36Mb SigmaSIO DDR-IITM Burst of 2 SRAM 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Simultaneous Read and Write SigmaSIO™ Interface JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time DLL circuitry for wide output data valid window and future frequency scaling Burst of 2 Read and Write 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ mode pin for programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package RoHS-compliant 165-bump BGA package available SigmaSIO™ Family Overview GS8342S08/09/18/36BD are built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748...