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CD82C87H Dataheets PDF



Part Number CD82C87H
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS Octal Inverting Bus Transceiver
Datasheet CD82C87H DatasheetCD82C87H Datasheet (PDF)

82C87H March 1997 CMOS Octal Inverting Bus Transceiver Description The Intersil 82C87H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C87H provides a full eight-bit bi-directional bus interface in a 20 pin package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C87H has gated inputs, eliminating.

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82C87H March 1997 CMOS Octal Inverting Bus Transceiver Description The Intersil 82C87H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C87H provides a full eight-bit bi-directional bus interface in a 20 pin package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C87H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation. The 82C87H provides inverted data at the outputs. Features • Full Eight Bit Bi-Directional Bus Interface • Industry Standard 8287 Compatible Pinout • High Drive Capability - B Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA - A Side IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA • Three-State Inverting Outputs • Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max. • Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors • Single 5V Power Supply • Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA • Operating Temperature Range - C82C87H . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC - I82C87H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C87H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Ordering Information PART NUMBERS 5MHz CP82C87H-5 IP82C87H-5 CS82C87H-5 IS82C87H-5 CD82C87H-5 ID82C87H-5 MD82C87H-5/B 59628757702RA MR82C87H-5/B 596287577022A 8MHz PACKAGE TEMP. RANGE 0oC to +70oC -40oC 0oC to +85oC PKG. NO. E20.3 E20.3 N20.35 N20.35 F20.3 CP82C87H 20 Ld PDIP IP82C87H CS82C87H 20 Ld PLCC IS82C87H CD82C87H 20 Ld CERDIP ID82C87H SMD # 20 Pad CLCC SMD # to +70oC +85oC -40oC 0oC to to +70oC -40oC to +85oC F20.3 -55oC to +125oC F20.3 F20.3 -55oC to +125oC J20.A J20.A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2978.1 4-325 82C87H Pinouts 82C87H (PDIP, CERDIP) TOP VIEW 82C87H (PLCC, CLCC) TOP VIEW VCC A2 A1 A0 B0 TRUTH TABLE T X H L OE H L L A Hi-Z I O B Hi-Z O I A0 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 OE 9 GND 10 20 VCC 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 T A6 7 A7 8 A3 4 A4 5 A5 6 3 2 1 20 19 18 B1 17 B2 16 B3 15 B4 14 B5 H L I O X Hi-Z = Logic One = Logic Zero = Input Mode = Output Mode = Don’t Care = High Impedance PIN NAMES 9 OE 10 GND 11 T 12 B7 13 B6 PIN A0-A7 B0-B7 T OE DESCRIPTION Local Bus Data I/O Pins System Bus Data I/O Pins Transmit Control Input Active Low Output Enable 4-326 82C87H Functional Diagram A0 B0 Decoupling Capacitors The transient current required to charge and discharge the 300pF load capacitance specified in the 82C86H/87H data sheet is determined by: I = C L ( dv ⁄ dt ) (EQ. 4) A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 Assuming that all outputs change state at the same time and that dv/dt is constant; (V CC × 80% ) I = C L -----------------------------------tR ⁄ tF (EQ. 5) where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight outputs. I = ( 80 × 300 × 10 = 480mA – 12 ) × ( 5.0V × 0.8 ) ⁄ ( 20 × 10 –9 ) (EQ. 6) OE T Gated Inputs During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance (“float” condition), it could create an indeterminate logic state at the inputs and cause a disruption in device operation. The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C87H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-Channel and lower N-Channel (See Figures 1 and 2). No current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device. D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10µ.


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