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CD82C88 Dataheets PDF



Part Number CD82C88
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS Bus Controller
Datasheet CD82C88 DatasheetCD82C88 Datasheet (PDF)

82C88 March 1997 CMOS Bus Controller Description The Intersil 82C88 is a high performance CMOS Bus Controller manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C88 provides the control and command timing signals for 80C86, 80C88, 8086, 8088, 8089, 80186, and 80188 based systems. The high output drive capability of the 82C88 eliminates the need for additional bus drivers. Static CMOS circuit design insures low operating power. The Intersil advanced SAJI process .

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82C88 March 1997 CMOS Bus Controller Description The Intersil 82C88 is a high performance CMOS Bus Controller manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C88 provides the control and command timing signals for 80C86, 80C88, 8086, 8088, 8089, 80186, and 80188 based systems. The high output drive capability of the 82C88 eliminates the need for additional bus drivers. Static CMOS circuit design insures low operating power. The Intersil advanced SAJI process results in performance equal to or greater than existing equivalent products at a significant power savings. Features • Compatible with Bipolar 8288 • Performance Compatible with: - 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz) - 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz) - 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz) - 8089 • Provides Advanced Commands for Multi-Master Busses • Three-State Command Outputs • Bipolar Drive Capability • Scaled SAJI IV CMOS Process • Single 5V Power Supply • Low Power Operation - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max) - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max) • Operating Temperature Ranges - C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC - I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Ordering Information PART NUMBER CP82C88 CP82C88-10 IP82C88 CS82C88 IS82C88 CD82C88 ID82C88 MD82C88/B 8406901RA MR82C88/B 84069012A SMD# 20 Pad CLCC SMD# -55oC to +125oC 20 Ld PLCC 20 Ld CERDIP PACKAGE 20 Ld PDIP TEMPERATURE RANGE 0oC to +70oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC -55oC to +125oC PKG. NO. E20.3 E20.3 E20.3 N20.35 N20.35 F20.3 F20.3 F20.3 F20.3 J20.A J20.A Pinouts 20 LEAD PDIP, CERDIP TOP VIEW IOB CLK S1 DT/ R ALE AEN MRDC AMWC MWTC 1 2 3 4 5 6 7 8 9 20 VCC 19 S0 18 S2 17 MCE/PDEN 16 DEN 15 CEN 14 INTA 13 IORC 12 AIOWC 11 IOWC DT/ R ALE AEN MRDC AMWC 4 5 6 7 8 9 MWTC 10 GND 11 IOWC 12 AIOWC 13 IORC 20 LEAD PLCC, CLCC TOP VIEW CLK VCC 20 IOB S1 S0 19 18 S2 17 MCE/PDEN 16 DEN 15 CEN 14 INTA 3 2 1 GND 10 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2979.1 4-333 82C88 Functional Diagram S0 S1 S2 MRDC MWTC AMWC IORC IOWC AIOWC INTA CLK CONTROL INPUT AEN CEN IOB CONTROL LOGIC CONTROL SIGNAL GENERATOR DT/R DEN MCE/PDEN ALE ADDRESS LATCH, DATA TRANSCEIVER, AND INTERRUPT CONTROL SIGNALS STATUS DECODER COMMAND SIGNAL GENERATOR MULTIBUSTM COMMAND SIGNALS VCC GND Pin Description PIN SYMBOL VCC GND S0, S1, S2 NUMBER 20 10 19, 3, 18 I TYPE DESCRIPTION VCC: The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling. GROUND. STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The 82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins are not in use (passive), command outputs are held HIGH (See Table1). CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock generator and serves to establish when command/control signals are generated. ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent D type latches, such as the 82C82 and 82C83H. DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This signal is active HIGH. DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory). ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH). COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled. INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections). CLK 2 I ALE 5 O DEN 16 O DT/R 4 O AEN 6 I CEN 15 I IOB 1 I Intel™ is a Registered Trademark of Intel Corporation 4-334 82C88 Pin Description PIN SYMBOL AIOWC NUMBER 12 (Continued) TYPE O DESCRIPTION ADVANCE.


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