DTMF Transceiver. MT8880C Datasheet


MT8880C Transceiver. Datasheet pdf. Equivalent


MT8880C


Integrated DTMF Transceiver
ISO2 - CMOS MT8880C Integrated DTMF Transceiver
Data Sheet

Features
• Complete DTMF transmitter/receiver • Central office quality • Low power consumption • Microprocessor port • Adjustable guard time • Automatic tone burst mode • Call progress mode
Applications
• Credit card systems • Paging systems • Repeater systems/mobile radio • Interconnect dialers • Personal computers
Description
The MT8880C is a monolithic DTMF transceiver with call progress filter. It is fabricated in Zarlink Semiconductor’s ISO2-CMOS technology, which

September 2005

Ordering Information

MT8880CE

20 Pin PDIP

Tubes

MT8880CS MT8880CN MT8880CP MT8880CP1 MT8880CS1 MT8880CE1 MT8880CN1 MT8880CSR MT8880CPR

20 Pin SOIC 24 Pin SSOP 28 Pin PLCC 28 Pin PLCC* 20 Pin SOIC* 20 Pin PDIP* 24 Pin SSOP* 20 Pin SOIC 28 Pin PLCC

Tubes Tubes Tubes Tubes Tubes Tubes Tubes Tape & Reel Tape & Reel

MT8880CPR1 28 Pin PLCC* MT8880CSR1 20 Pin SOIC*

Tape & Reel Tape & Reel

*Pb Free Matte Tin

-40°C to...



MT8880C
ISO2 - CMOS MT8880C
Integrated DTMF Transceiver
Data Sheet
Features
• Complete DTMF transmitter/receiver
• Central office quality
• Low power consumption
• Microprocessor port
• Adjustable guard time
• Automatic tone burst mode
• Call progress mode
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers
Description
The MT8880C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in Zarlink
Semiconductor’s ISO2-CMOS technology, which
September 2005
Ordering Information
MT8880CE
20 Pin PDIP
Tubes
MT8880CS
MT8880CN
MT8880CP
MT8880CP1
MT8880CS1
MT8880CE1
MT8880CN1
MT8880CSR
MT8880CPR
20 Pin SOIC
24 Pin SSOP
28 Pin PLCC
28 Pin PLCC*
20 Pin SOIC*
20 Pin PDIP*
24 Pin SSOP*
20 Pin SOIC
28 Pin PLCC
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
MT8880CPR1 28 Pin PLCC*
MT8880CSR1 20 Pin SOIC*
Tape & Reel
Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
provides low power dissipation and high reliability. The
DTMF receiver is based upon the industry standard
MT8870 monolithic DTMF receiver; the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones. A standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors.
TONE
D/A
Converters
IN+
IN-
GS
OSC1
OSC2
Tone Burst
Gating Cct.
+ Dial
- Tone
Filter
Oscillator
Circuit
Bias
Circuit
Control
Logic
High Group
Filter
Low Group
Filter
Control
Logic
Row and
Column
Counters
Digital
Algorithm
and Code
Converter
Steering
Logic
Transmit Data
Register
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Data
Bus
Buffer
Interrupt
Logic
I/O
Control
VDD VRef VSS
ESt St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved.
D0
D1
D2
D3
IRQ/CP
Φ2
CS
R/W
RS0

MT8880C
MT8880C
Data Sheet
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
20 VDD
19 St/GT
18 ESt
17 D3
16 D2
15 D1
14 D0
13 IRQ/CP
12 Φ2
11 RS0
20 PIN PLASTIC DIP/SOIC
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
11
12
24 VDD
23 St/GT
22 ESt
21 D3
20 D2
19 D1
18 D0
17 NC
16 NC
15 IRQ/CP
14 Φ2
13 RS0
NC
VRef
VSS
OSC1
OSC2
NC
NC
5
6
7
8
9
10
11
24 PIN SSOP
28 PIN PLCC
Figure 2 - Pin Connections
25 NC
24 NC
23 NC
22 D3
21 D2
20 D1
19 D0
Pin Description
Pin #
20 24 28
Name
Description
1 1 1 IN+ Non-inverting op-amp input.
2 2 2 IN- Inverting op-amp input.
3 3 4 GS Gain Select. Gives access to output of front end differential amplifier for connection of feedback
resistor.
44
55
66
6 VRef Reference Voltage output, nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 13).
7 VSS Ground input (0 V).
8 OSC1 DTMF clock/oscillator input. Connect a 4.7 Mresistor to VSS if crystal oscillator is used.
77
9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
8 10 12 TONE Tone output (DTMF or single tone).
9 11 13 R/W Read/Write input. Controls the direction of data transfer to and from the MPU and the transceiver
registers. TTL compatible.
10 12 14 CS Chip Select, TTL input (CS=0 to select the chip).
11 13 15 RS0 Register Select input. See register decode table. TTL compatible.
12 14 17 Φ2 System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the device
is not being accessed.
13 15
18 IRQ/C Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has been
P selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal representative
of the input signal applied at the input op-amp. The input signal must be within the bandwidth
limits of the call progress filter. See Figure 8.
14- 18-21 19-22 D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ2 is low.
17
2
Zarlink Semiconductor Inc.




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)