High-performance Electrically Erasable Programmable Logic Device
Features
• Industry Standard Architecture – Low-cost Easy-to-use Software Tools
• High-speed, Electrically Erasable Prog...
Description
Features
Industry Standard Architecture – Low-cost Easy-to-use Software Tools
High-speed, Electrically Erasable Programmable Logic Devices CMOS and TTL Compatible Inputs and Outputs
– Input and I/O Pull-up Resistors Advanced Flash Technology
– Reprogrammable – 100% Tested High-reliability CMOS Process – 20 year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200mA Latchup Immunity Full Military Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts PCI Compliant
Figure 0-1. Logic Diagram
Figure 0-2. Pin Configurations
All Pinouts Top View
Pin Name CLK IN I/O * VCC
Function Clock Logic Inputs Bidirectional Buffers No Internal Connection +5V Supply
CLK/IN IN IN IN IN IN IN IN IN IN IN
GND
TSSOP
1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13
VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN
DIP/SOIC
CLK/IN IN IN IN IN IN IN IN IN IN IN
GND
1 2 3 4 5 6 7 8 9 10 11 12
24 VCC 23 ...
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