S25FL512S

S25FL512S 512 Mb (64 MB), 3.0 V SPI Flash Memory S25FL512S, 512 Mb (64 MB), 3.0 V SPI Flash Memory Features  CMOS 3.0 V Core with versatile I/O  SPI with Multi-I/O  Density ❐ 512 Mb (64 MB)  SPI ❐ SPI Clock polarity and phase modes 0 and 3 ❐ DDR option ❐ Extended Addressing: 32-bit address ❐ Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families ❐ Multi I/O Command set and footprint compatible with the S25FL-P SPI family  READ Commands ❐ Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR ❐ AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address ❐ Common Flash Interface (CFI) data for configuration infor- mation.  Programming (1.5 MBps) ❐ 512-byte Page Programming buffer ❐ Quad-Input Page Programming (QPP) for slow clock sys- tems ❐ Automatic ECC -internal hardware Error Correction Code generation with single bit error correction  Erase (0.5 to 0.65 MBps) ❐ Uniform 256-KB sectors  Cycling Endurance ❐ 100,000 Program-Erase Cycles, minimum Logic Block Diagram  Data Retention ❐ 20-Year Data Retention, minimum  Security Features ❐ OTP array of 1024 bytes ❐ Block Protection: Status Register bits to control protection against program or erase of a contiguous range of sectors. Hardware and software control options ❐ Advanced Sector Protection (ASP) Individual sector protection controlled by boot code or password  Cypress 65 nm MirrorBit® Technology with Eclipse™ Architec...