CY7C1276V18

CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth ■ 4-Word Burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz ■ Read latency of 2.5 clock cycles ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate Port Selects for depth expansion ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ Available in x8, x9, x18, and x36 configurations ■ Full data coherency providing most current data ■ Core VDD = 1.8V ...