1.8V Synchronous Pipelined SRAM
CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18
36-Mbit DDR-II SRAM 4-Word Burst Architecture
Features
• 36-Mbit d...
Description
CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18
36-Mbit DDR-II SRAM 4-Word Burst Architecture
Features
36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300-MHz clock for high bandwidth 4-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches Echo clocks (CQ and CQ) simplify data capture in
high-speed systems Synchronous internally self-timed writes 1.8V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.4V–VDD) Available in 165-ball FBGA package (15 x 17 x 1.4 mm) Offered in both lead-free and non lead-free packages JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement
Configurations
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