PRELIMINARY
CY7C1304DV25
9-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture
Features
Separate independent Read and Write data ports — Supports concurrent transactions
167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time
4-Word Burst for reducing the address bus frequency Double Data Rate (DDR) interfaces on both Read and
Writ...
