CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Features
■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) ...
