CY7C1394BV18

CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self-timed writes ■ 1.8V core power supply with HSTL inputs and outputs ■ Variable drive HSTL output buffers ■ Expanded HSTL output voltage (1.4V–VDD) ■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ JTAG 1149.1 compatible test access port ■ Delay Lock Loop (DLL) for accurate data placement Configurati...