MC10E156

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 MuxĆLatch The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. 950ps Max. D to Output 850ps Max. LEN to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors MC10E156 MC100E156 3-BIT 4:1 MUX-LATCH Pinout: 28-Lead PLCC (Top View) D1b D1a D2d D2c D2b D2a VCCO 25 24 23 22 21 20 19 SEL0 26 18 Q2 SEL1 27 17 Q2 MR 28 16 VCC VEE 1 15 Q1 LEN1 2 LEN2 3 14 Q1 13 VCCO D1c 4 12 Q0 5 6 7 8 9 10 11 D1d D0a D0b D0c D0d VCCO Q0 * All VCC and VCCO pins are tied toge...