Document
CD22103A
Data Sheet January 1997 File Number
1310.3
CMOS HDB3 (High Density Bipolar 3) Transcoder for 2.048/8.448Mb/s Transmission Applications
The CD22103A is an LSI SOS integrated circuit which performs the HDB3 transmission coding and reception decoding functions with error detection. It is used in 2.048Mb/s and 8.448Mb/s transmission applications. The CD22103A performs HDB3 coding and decoding for data rates from 50Kb/s to 10Mb/s in a manner consistent with CCITT G703 recommendations. HDB3 transmission coding/reception decoding with code error detection is performed in independent coder and decoder sections. All transmitter and receiver inputs/outputs are TTL compatible. The HDB3 transmitter coder codes an NRZ binary unipolar input signal (NRZ-IN) and a synchronous transmission clock (CTX) into two HDB3 binary unipolar RZ output signals (+HDB3 OUT, -HDB3 OUT). The TTL compatible output signals +HDB3 OUT, -HDB3 OUT are externally mixed to generate ternary bipolar HDB3 signals for driving transmission lines. The receiver decoder converts binary unipolar inputs (+HDB3 IN, -HDB3 IN), which were externally split from ternary bipolar HDB3 signals, and a synchronous clock signal (CRX) into binary unipolar NRZ signals (NRZ-OUT). The CD22103A operates with a 5V ±10% power supply voltage over the full military temperature range at data rates from 50Kb/s up to 10Mb/s.
Features
• HDB3 Coding and Decoding for Data Rates from 50Kb/s to 10Mb/s in a Manner Consistent with CCITT G703 Recommendations • HDB3/AMI Transmission Coding/Reception Decoding with Code Error Detection is Performed in Independent Coder and Decoder Sections • All Transmitter and Receiver Inputs/Outputs are TTL Compatible • Internal Loop Test Capability • Pin and Functionally Compatible with Type MJ1471
Ordering Information
PART NUMBER CD22103AD CD22103AE TEMP. RANGE (oC) -55 to 125 -40 to 85 PACKAGE 16 Ld SBDIP 16 Ld PDIP PKG. NO. D16.3 E16.3
Pinout
CD22103A (PDIP, SBDIP) TOP VIEW
NRZ-IN 1 CTX 2 HDB3/AMI 3 NRZ-OUT 4 CRX 5 RAIS 6 AIS 7 VSS 8 16 VDD 15 +HDB3 OUT 14 -HDB3 OUT 13 +HDB3 IN 12 LTE 11 -HDB3 IN 10 CKR 9 ERR
Block Diagram
HDB3/AMI CTX NRZ-IN ENCODER IN LTE +HDB3 IN -HDB3 IN CRX REQUIRES CLOCK RECOVERY CIRCUIT RECEIVER DECODER NRZ-OUT TRANSMITTER CODER +HDB3 OUT -HDB3 OUT CKR
DECODER
ERROR DETECT AIS DETECT
ERR
AIS
RAIS
68
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
CD22103A
Absolute Maximum Ratings
Supply Voltage (VDD) (Voltages referenced to VSS Terminal) . . . . . . . . . . . . . -0.5 to 8V Supply Voltage Range For TA = Full Package Temperature Range . . . . . . . . . . . . 4.5V to 5.5V Input Voltage (All Inputs) . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5V Input Current (Any One Input) . . . . . . . . . . . . . . . . . . . . . . . . . . .±10mA Power Dissipation For TA = -40oC to 60oC (Package Type E). . . . . . . . . .