W255 Data Sheet PDF | Cypress Semiconductor





(Datasheet) W255 PDF Download

Part Number W255
Description 200-MHz 24-Output Buffer
Manufacture Cypress Semiconductor
Total Page 10 Pages
PDF Download Download W255 Datasheet PDF

Features: W255 200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS Features Functional Description • One input to 24-outpu t buffer/driver • Supports up to 4 DD R DIMMs or 3 SDRAM DIMMS • One additi onal output for feedback • SMBus inte rface for individual output control • Low skew outputs (< 100 ps) • Suppor ts 266-, 333-, and 400-MHz DDR SDRAM Dedicated pin for power management su pport • Space-saving 48-pin SSOP pack age The W255 is a 3.3V/2.5V buffer des igned to distribute high-speed clocks i n PC applications. The part has 24 outp uts. Designers can configure these outp uts to support four unbuffered DDR DIMM S or to support three unbuffered standa rd SDRAM DIMMs and two DDR DIMMS. The W 255 can be used in conjunction with the W250 or similar clock synthesizer for the VIA Pro 266 chipset. The W255 also includes an SMBus interface which can e nable or disable each output clock. On power-up, all output clocks are enabled (internal pull up). Block Diagram BUF_IN SDATA SCLOCK SMBus.

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W255 datasheet
W255
200-MHz 24-Output Buffer for 4 DDR
or 3 SDRAM DIMMS
Features
Functional Description
• One input to 24-output buffer/driver
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266-, 333-, and 400-MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 48-pin SSOP package
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Block Diagram
BUF_IN
SDATA
SCLOCK
SMBus
Decoding
PWR_DWN#
SEL_DDR
Power Down Control
Pin Configuration[1]
FBOUT
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
FBOUT
VDD3.3_2.5
GND
DDR2T_SDRAM2 DDR0T_SDRAM10
DDR2C_SDRAM3 DDR0C_SDRAM11
DDR3T_SDRAM4 DRR1T_SDRAM0
DDR3C_SDRAM5 DDR1C_SDRAM1
DDR4T_SDRAM6
VDD3.3_2.5
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
GND
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
DDR6T
BUF_IN
DDR6C
GND
DDR7T
DDR7C
DDR8T
DDR8C
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR9T
DDR4C_SDRAM7
DDR9C
DDR10T
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
DDR10C
SDATA
SSOP
Top View
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
DDR11T
DDR11C
Note:
1. Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07255 Rev. *D
Revised April 28, 2005

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