high-speed CMOS MirrorBit NOR flash devices
S26KL512S/S26KS512S S26KL256S/S26KS256S S26KL128S/S26KS128S
512 Mb (64 MB)/256 Mb (32 MB)/ 128 Mb (16 MB), 1.8V/3.0V Hyp...
Description
S26KL512S/S26KS512S S26KL256S/S26KS256S S26KL128S/S26KS128S
512 Mb (64 MB)/256 Mb (32 MB)/ 128 Mb (16 MB), 1.8V/3.0V HyperFlash™ Family
Features
■ 3.0V I/O, 11 bus signals ❐ Single ended clock
■ 1.8V I/O, 12 bus signals ❐ Differential clock (CK, CK#)
■ Chip Select (CS#)
■ 8-bit data bus (DQ[7:0])
■ Read-Write Data Strobe (RWDS) ❐ HyperFlash™ memories use RWDS only as a Read Data Strobe
■ Up to 333 MBps sustained read throughput
■ DDR – two data transfers per clock
■ 166-MHz clock rate (333 MBps) at 1.8V VCC
■ 100-MHz clock rate (200 MBps) at 3.0V VCC
■ 96-ns initial random read access time ❐ Initial random access read latency: 5 to 16 clock cycles
■ Sequential burst transactions
■ Configurable Burst Characteristics ❐ Wrapped burst lengths: 16 bytes (8 clocks) 32 bytes (16 clocks) 64 bytes (32 clocks) ❐ Linear burst ❐ Hybrid option: one wrapped burst followed by linear burst ❐ Wrapped or linear burst type selected in each transaction ❐ Configurable output drive strength
Low Power Modes ❐ Active Clock Stop During Read: 12 mA, no wake-up required ❐ Standby: 25 µA (typical), no wake-up required ❐ Deep Power-Down: 8 µA (typical) 300 µs wake-up required
INT# output to generate external interrupt
❐ Busy to Ready Transition ❐ ECC detection RSTO# output to generate system level power-on reset
❐ User configurable RSTO# Low period 512-byte Program Buffer
Sector Erase
❐ Uniform 256-KB sectors ❐ Optional Eight 4-KB Parameter Sectors (32 KB total) Advanced Sector Prot...
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