9FGL02 Datasheet: 2-output 3.3V PCIe Clock Generator





9FGL02 2-output 3.3V PCIe Clock Generator Datasheet

Part Number 9FGL02
Description 2-output 3.3V PCIe Clock Generator
Manufacture IDT
Total Page 19 Pages
PDF Download Download 9FGL02 Datasheet PDF

Features: 2-output 3.3V PCIe Clock Generator 9FGL 02 DATASHEET Description The 9FGL02 d evices are 3.3V members of IDT's 3.3V F ull-Featured PCIe family. The devices h ave 2 output enables for clock manageme nt and support 2 different spread spect rum levels in addition to spread off. T he 9FGL02 supports PCIe Gen1-4 Common C locked architectures (CC) and PCIe Sepa rate Reference no-Spread (SRnS) and Sep arate Reference Independent Spread (SRI S) clocking architectures. The 9FGL02P1 can be programmed with a user-defined power up default SMBus configuration. R ecommended Application PCIe Gen1-4 cloc k generation for Riser Cards, Storage, Networking, JBOD, Communications, Acces s Points Output Features • 2 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs • 9FGL0241 default ZOUT = 100 • 9FGL0251 default ZOUT = 85 • 9FGL0 2P1 factory programmable defaults • 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL) support • Easy AC-coupling to other logic families, see IDT application note AN-891 Key Speci.

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2-output 3.3V PCIe Clock Generator
9FGL02
DATASHEET
Description
The 9FGL02 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 2 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL02
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL02P1 can be programmed with a
user-defined power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
2 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
9FGL0241 default ZOUT = 100
9FGL0251 default ZOUT = 85
9FGL02P1 factory programmable defaults
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC-compliant
PCIe Gen2-3 SRIS-compliant
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF 12k-20M phase jitter is <2ps rms when SSC is off
REF phase jitter is <300fs rms (SSC off) and < 1.5ps RMS
(SSC on)
±100ppm frequency accuracy on all clocks
Block Diagram
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 8 resistors compared to standard
PCIe devices
112mW typical power consumption (@3.3V); eliminates
thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
33, 85 or 100output impedance for each output
spread spectrum amount
input frequency
41 and 51 devices contain default configuration; SMBus
interface not required for device operation
P1 device allows factory programming of customer-defined
input/output frequencies and SMBus power up default;
allows exact optimization to customer requirements
OE# pins; support DIF power management
8MHz - 40MHz input frequency with 9FGL02P1 device
(25MHz default); flexibility
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
DIF outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
y
vOE(1:0)#
XIN/CLKIN_25
2
REF
603-25-150JA4I 25MHz
X2
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SSC Capable
PLL
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL02 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

                    
                    






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