9FG1901H Datasheet | Frequency Generator





(Datasheet) 9FG1901H Datasheet PDF Download

Part Number 9FG1901H
Description Frequency Generator
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9FG1901H Datasheet PDF

Features: Frequency Gearing Clock for CPU, PCIe Ge n1 & FBD DATASHEET 9FG1901H Descripti on Features/Benefits The 9FG1901H fol lows the Intel DB1900G Differential Buf fer Specification. This buffer provides 19 output clocks for CPU Host Bus, PCI -Express, or Fully Buffered DIMM applic ations. The outputs are configured with two groups. Both groups, DIF_(16:0) an d DIF_(18:17) can be equal to or have a gear ratio to the input clock. A diffe rential CPU clock from a CK410B+ main c lock generator, such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H ca n provide outputs up to 400MHz. • • • • • • Power up default is all outputs in 1:1 mode DIF_(16:0) can be “gear-shifted” from the inpu t CPU Host Clock DIF_(18:17) can be “ gear-shifted” from the input CPU Host Clock Spread spectrum compatible Suppo rts output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode Key Specifications • VDDA controlled power down mode • DI.

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Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
DATASHEET
9FG1901H
Description
Features/Benefits
The 9FG1901H follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H
can provide outputs up to 400MHz.
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Key Specifications
• VDDA controlled power down mode
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
OE(16:5)#, 13
OE_01234#
CLK_IN
CLK_IN#
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(18:17)
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(16:0)
IREF
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1
1386A - 02/02/10

                    
                    






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