9FGV0841 Datasheet | 8-Output Very Low-Power PCIe Gen1-4 Clock Generator





(Datasheet) 9FGV0841 Datasheet PDF Download

Part Number 9FGV0841
Description 8-Output Very Low-Power PCIe Gen1-4 Clock Generator
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9FGV0841 Datasheet PDF

Features: 8-O/P 1.8V PCIe Gen 1-2-3 Clock Generato r w/Zo=100ohms 9FGV0841 DATASHEET Des cription The 9FGV0841 is a member of ID T's SOC-Friendly 1.8V Very-Low-Power PC Ie clock family. It has integrated outp ut terminations providing Zo=100 for direction connection to 100 transmi ssion lines. The device has 8 output en ables for clock management, 2 different spread spectrum levels in addition to spread off and 2 selectable SMBus addre sses. Recommended Application 1.8V PCIe Gen1-2-3 clock generator Output Featur es • 8 - 100MHz Low-Power (LP) HCSL D IF pairs w/Zo=100 • 1 - 1.8V LVCMO S REF output w/Wake-On-LAN (WOL) suppor t Key Specifications • DIF cycle-to-c ycle jitter <50ps • DIF output-to-out put skew <50ps • DIF phase jitter is PCIe Gen1-2-3 compliant • REF phase j itter is < 1.5ps RMS Block Diagram Fea tures/Benefits • Direct connection to 100Ω transmission lines; saves 32 re sistors compared to standard PCIe devic es • 62mW typical power consumption; reduced thermal concerns.

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8-Output Very Low-Power PCIe Gen1-4 Clock
Generator with Zo = 100ohms
9FGV0841
DATASHEET
Description
The 9FGV0841 is a member of IDT's SOC-friendly 1.8V very
low-power PCIe clock family. It has integrated output
terminations providing Zo = 100for direction connection to
100transmission lines. The device has 8 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off, and 2 selectable SMBus addresses.
Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
8 100MHz Low-Power HCSL (LP-HCSL) DIF pairs with
Zo = 100
1 1.8V LVCMOS REF output with Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF phase jitter is PCIe Gen1–4 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
Features
Direct connection to 100transmission lines; saves 32
resistors compared to standard PCIe devices
62mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 6 x 6 mm 48-VFQFPN; minimal board space
vOE(7:0)#
XIN /CLKIN _25
X2
8
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0841 JANUARY 24, 2018
1 ©2018 Integrated Device Technology, Inc.

                    
                    






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