9FGU0241 Datasheet: 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator





9FGU0241 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator Datasheet

Part Number 9FGU0241
Description 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
Manufacture IDT
Total Page 15 Pages
PDF Download Download 9FGU0241 Datasheet PDF

Features: 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator w/Zo=100ohms 9FGU0241 DATASHEET Desc ription The 9FGU0241 is a member of IDT 's 1.5V Ultra-Low-Power PCIe clock fami ly with integrated output terminations providing Zo=100Ω. The device has 2 o utput enables for clock management, 2 d ifferent spread spectrum levels in addi tion to spread off and 2 selectable SMB us addresses. Recommended Application 1 .5V PCIe Gen1-2-3 clock generator Outpu t Features • 2 - 100MHz Low-Power (LP ) HCSL DIF pairs w/Zo=100 • 1 - 1. 5V LVCMOS REF output w/Wake-On-LAN (WOL ) support Key Specifications • DIF cy cle-to-cycle jitter <50ps • DIF outpu t-to-output skew <50ps • DIF phase ji tter is PCIe Gen1-2-3 compliant • REF phase jitter is < 3.0ps RMS Features/ Benefits • Direct connection to 100oh m transmission lines; saves 16 resistor s compared to standard PCIe devices • 23mW typical power consumption; reduce d thermal concerns • OE# pins; suppor t DIF power management • Programmable Slew rate for each outp.

Keywords: 9FGU0241, datasheet, pdf, IDT, 2, O/P, 1.5V, PCIe, Gen1-2-3, Clock, Generator, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0241
DATASHEET
Description
The 9FGU0241 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 2 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
2 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
23mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
vOE(1:0)#
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF1
DIF0
9FGU0241 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

                    
                    






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)