9FGU0441 Data Sheet PDF | IDT





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Part Number 9FGU0441
Description 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
Manufacture IDT
Total Page 15 Pages
PDF Download Download 9FGU0441 Datasheet PDF

Features: 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator w/Zo=100ohms 9FGU0441 DATASHEET Desc ription The 9FGU0441 is a member of IDT 's 1.5V Ultra-Low-Power PCIe clock fami ly with integrated output terminations providing Zo=100Ω. The device has 4 o utput enables for clock management, 2 d ifferent spread spectrum levels in addi tion to spread off and 2 selectable SMB us addresses. Recommended Application 1 .5V PCIe Gen1-2-3 clock generator Outpu t Features • 4 - 100MHz Low-Power (LP ) HCSL DIF pairs w/Zo=100ohms • 1 - 1 .5V LVCMOS REF output w/Wake-On-LAN (WO L) support Key Specifications • DIF c ycle-to-cycle jitter <50ps • DIF outp ut-to-output skew <50ps • DIF phase j itter is PCIe Gen1-2-3 compliant • RE F phase jitter is < 3.0ps RMS Block Dia gram Features/Benefits • Direct conn ection to 100ohm transmission lines; sa ves 16 resistors compared to standard P CIe devices • 39mW typical power cons umption; reduced thermal concerns • O E# pins; support DIF power management • Programmable Slew rat.

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9FGU0441 datasheet
4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0441
DATASHEET
Description
The 9FGU0441 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 4 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
4 - 100MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100ohms
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
39mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
REF1.5
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF3
DIF2
DIF1
DIF0
9FGU0441 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

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