9FGU0841 Datasheet | 8-output 1.5V PCIe Gen1-2-3 Clock Generator





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Part Number 9FGU0841
Description 8-output 1.5V PCIe Gen1-2-3 Clock Generator
Manufacture IDT
Total Page 16 Pages
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Features: 8-output 1.5V PCIe Gen1-2-3 Clock Genera tor w/Zo=100ohms 9FGU0841 DATASHEET G eneral Description The 9FGU0841 is a me mber of IDT's 1.5V Ultra-Low-Power PCIe clock family with integrated output te rminations providing Zo=100Ω. The dev ice has 8 output enables for clock mana gement, 2 different spread spectrum lev els in addition to spread off and 2 sel ectable SMBus addresses. Recommended Ap plication • 1.5V PCIe Gen1-2-3 Clock Generator Output Features • 8 - 100MH z Low-Power (LP) HCSL DIF pairs w/Zo=10 0ohms • 1 - 1.5V LVCMOS REF output w/ Wake-On-LAN (WOL) support Key Specifica tion • DIF cycle-to-cycle jitter <50p s • DIF output-to-output skew < 60ps • DIF phase jitter is PCIe Gen1-2-3 c ompliant • REF phase jitter is < 3.0p s RMS Functional Block Diagram Feature s/Benefits • Direct connection to 100 ohm transmission lines; saves 32 resist ors compared to standard PCIe devices 50mW typical power consumption; redu ced thermal concerns • Outputs can optionally be supplied fro.

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8-output 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0841
DATASHEET
General Description
The 9FGU0841 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 8 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
Output Features
8 - 100MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100ohms
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specification
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 60ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Functional Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 32
resistors compared to standard PCIe devices
50mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line length
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EM
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGU0841 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

                    
                    






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