9FGV0631C Datasheet | 6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator





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Part Number 9FGV0631C
Description 6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator
Manufacture IDT
Total Page 16 Pages
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Features: 6-O/P 1.8V PCIe Gen 1-2-3 Clock Generato r 9FGV0631C DATASHEET General Descrip tion The 9FGV0631C is a member of IDT's SOC-Friendly 1.8V Very-Low-Power PCIe clock family. The device has 6 output e nables for clock management, 2 differen t spread spectrum levels in addition to spread off and 2 selectable SMBus addr esses. Recommended Application 1.8V PCI e Gen 1-2-3 Clock Generator Output Feat ures • 6 - 100MHz Low-Power (LP) HCSL DIF pairs • 1 - 1.8V LVCMOS REF outp ut w/Wake-On-LAN (WOL) support Key Spec ifications • DIF cycle-to-cycle jitte r <50ps • DIF output-to-output skew < 50ps • DIF phase jitter is PCIe Gen1- 2-3 Compliant • REF phase jitter is < 1.5ps RMS Block Diagram Features/Benef its • LP-HCSL outputs; save 12 resist ors compared to standard PCIe devices 54mW typical power consumption; redu ced thermal concerns • Outputs can op tionally be supplied from any voltage b etween 1.05V and 1.8V; maximum power sa vings • OE# pins; support DIF power management • Programmab.

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6-Output Very Low-Power PCIe Gen 1-2-3-4
Clock Generator
9FGV0631C
DATASHEET
Description
The 9FGV0631C is a member of IDT's SOC-Friendly 1.8V
very low-power PCIe clock family. The device has 6 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off, and 2 selectable SMBus
addresses.
Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
6 100MHz Low-Power (LP) HCSL DIF pairs
1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3-4 compliant
REF phase jitter is <1.5ps RMS
Block Diagram
Features
LP-HCSL outputs; save 12 resistors compared to standard
PCIe devices
54mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 5 x 5 mm 40-VFQFPN; minimal board space
vOE(5:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0631C JUNE 23, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
                    






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