9FGV0641 Datasheet | 6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator





(Datasheet) 9FGV0641 Datasheet PDF Download

Part Number 9FGV0641
Description 6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9FGV0641 Datasheet PDF

Features: 6-O/P 1.8V PCIe Gen 1-2-3 Clock Generato r w/Zo=100ohms 9FGV0641 DATASHEET Gen eral Description The 9FGV0641 is a memb er of IDT's SOC-Friendly 1.8V Very-Low- Power PCIe clock family. The device has integrated 100 ohm output terminations providing direction connection to 100 ohm transmission lines. The device also has 6 output enables for clock managem ent and supports 2 different spread spe ctrum levels in addition to spread off. Recommended Application 1.8V PCIe Gen 1-2-3 Clock Generator Output Features 6 - 100MHz Low-Power (LP) HCSL DIF p airs w/Zo=100 • 1 - 1.8V LVCMOS RE F output w/Wake-On-LAN (WOL) support Ke y Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3 compliant • REF phase jitte r is <1.5ps RMS Block Diagram Features /Benefits • LP-HCSL outputs with inte grated terminations; save 24 resistors compared to standard PCIe devices • 5 4mW typical power consumption; reduced thermal concerns • Out.

Keywords: 9FGV0641, datasheet, pdf, IDT, 6-Output, Very, Low-Power, PCIe, Gen, 1-2-3-4, Clock, Generator, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

6-Output Very Low-Power PCIe Gen 1-2-3-4
Clock Generator with Zo=100ohms
9FGV0641
DATASHEET
Description
The 9FGV0641 is a member of IDT's SOC-Friendly 1.8V very
low-power PCIe clock family. The device has integrated 100
output terminations providing direction connection to 100
transmission lines. The device also has 6 output enables for
clock management and supports 2 different spread spectrum
levels in addition to spread off.
Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
6 100MHz Low-Power (LP) HCSL DIF pairs with Zo =
100
1 1.8V LVCMOS REF output with Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3-4 compliant
REF phase jitter is <1.5ps RMS
Features
LP-HCSL outputs with integrated terminations; save 24
resistors compared to standard PCIe devices
54mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 5 x 5 mm 40-VFQFPN; minimal board space
Block Diagram
vOE(5:0)#
XIN/CLKIN_25
X2
6
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0641 JUNE 23, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
                    






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)