9DB106 Data Sheet PDF | IDT





(Datasheet) 9DB106 PDF Download

Part Number 9DB106
Description Six Output Differential Buffer
Manufacture IDT
Total Page 14 Pages
PDF Download Download 9DB106 Datasheet PDF

Features: Six Output Differential Buffer for PCIe Gen 2 DATASHEET 9DB106 Description F eatures/Benefits The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clo cking requirements. The 9DB106 is drive n by a differential SRC output pair fro m an IDT CK410/CK505-compliant main clo ck generator. It attenuates jitter on t he input clock and has a selectable PLL bandwidth to maximize performance in s ystems with or without Spread-Spectrum clocking. An SMBus interface allows con trol of the PLL bandwidth and bypass op tions, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Expre ss Card applications. • • • • • CLKREQ# pin for outputs 1 and 4/ s upports Express Card applications PLL o r bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimiz es jitter peaking in downstream PLL's S pread Spectrum Compatible/tracks spread ing input clock for low EMI SMBus Inter face/unused outputs can be disabled Re commended Applications 6 Output Differential Buffer for PCIe Ge.

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9DB106 datasheet
Six Output Differential Buffer for PCIe Gen 2
DATASHEET
9DB106
Description
Features/Benefits
The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2
clocking requirements. The 9DB106 is driven by a differential SRC
output pair from an IDT CK410/CK505-compliant main clock
generator. It attenuates jitter on the input clock and has a selectable
PLL bandwidth to maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows control of
the PLL bandwidth and bypass options, while 2 clock request
(CLKREQ#) pins make the 9DB106 suitable for Express Card
applications.
CLKREQ# pin for outputs 1 and 4/ supports Express Card
applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
SMBus Interface/unused outputs can be disabled
Recommended Applications
6 Output Differential Buffer for PCIe Gen 2
Output Features
• 6 - 0.7V current mode differential output pairs (HCSL)
Key Specifications
• Cycle-to-cycle jitter < 50ps
• Output-to-output skew < 50 ps
Functional Block Diagram
CLKREQ1#
CLKREQ4#
CLK_INT
C LK_INC
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX1
PCIEX4
PCIEX(0,2,3,5)
IREF
IDT® Six Output Differential Buffer for PCIe Gen 2
1
9DB106 REV K 04/20/11

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