9DB1200C Datasheet: Twelve Output Differential Buffer





9DB1200C Twelve Output Differential Buffer Datasheet

Part Number 9DB1200C
Description Twelve Output Differential Buffer
Manufacture IDT
Total Page 14 Pages
PDF Download Download 9DB1200C Datasheet PDF

Features: DATASHEET Twelve Output Differential Bu ffer for PCIe Gen1/Gen2, QPI, and FBDIM M 9DB1200C Description DB1200 Rev 2.0 Intel Yellow Cover Device General Desc ription The ICS9DB1200 is an Intel DB12 00 Differential Buffer Specification de vice. This buffer provides 12 different ial clocks at frequencies ranging from 100MHz to 400 MHz. The ICS9DB1200 is dr iven by a differential output from a CK 410B+ or CK509B main clock generator. O utput Features • 12 - 0.7V current-mo de differential output pairs. • Suppo rts zero delay buffer mode and fanout m ode. • Bandwidth programming availabl e. • 100-400 MHz operation in PLL mod e • 33-400 MHz operation in Bypass mo de Features/Benefits • 3 selectable SMBus addresses for easy system expansi on • Spread spectrum modulation toler ant, 0 to -0.5% down spread and +/- 0.2 5% center spread • Supports undriven differential outputs in Power Down Mode for power management. Key Specificatio ns • Output cycle-cycle jitter < 50ps. • Output to output s.

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DATASHEET
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI,
and FBDIMM
9DB1200C
Description
DB1200 Rev 2.0 Intel Yellow Cover Device
General Description
The ICS9DB1200 is an Intel DB1200 Differential Buffer
Specification device. This buffer provides 12 differential clocks
at frequencies ranging from 100MHz to 400 MHz. The
ICS9DB1200 is driven by a differential output from a CK410B+
or CK509B main clock generator.
Output Features
• 12 - 0.7V current-mode differential output pairs.
• Supports zero delay buffer mode and fanout mode.
• Bandwidth programming available.
• 100-400 MHz operation in PLL mode
• 33-400 MHz operation in Bypass mode
Features/Benefits
• 3 selectable SMBus addresses for easy system expansion
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
• Supports undriven differential outputs in Power Down Mode
for power management.
Key Specifications
• Output cycle-cycle jitter < 50ps.
• Output to output skew: 50ps
• Phase jitter: PCIe Gen2 < 3.1ps rms
• Phase jitter: QPI < 0.5ps rms
• 64-pin TSSOP Package
• Available in RoHS compliant packaging
Functional Block Diagram
12
OE_(11:0)#
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
FS(2:0)
HIGH_BW#
BYPASS#/PLL
VTTPWRGD#/PD
ADR_SEL
SMBDAT
SMBCLK
CONTROL
LOGIC
M
U
X
12
DIF(11:0))
IREF
IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
1
1414F—06/30/10

                    
                    






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