9DB1233 Datasheet PDF Download, IDT





(PDF) 9DB1233 Datasheet Download

Part Number 9DB1233
Description Twelve Output Differential Buffer
Manufacture IDT
Total Page 15 Pages
PDF Download Download 9DB1233 Datasheet PDF

Features: Twelve Output Differential Buffer for PC Ie Gen3 DATASHEET 9DB1233 Recommended Application 12 output PCIe Gen3 zero-d elay/fanout buffer General Description The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being bac kwards compatible to PCIe Gen2 and Gen1 . The 9DB1233 is driven by a differenti al SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock ge nerator. It attenuates jitter on the in put clock and has a selectable PLL band width to maximize performance in system s with or without Spread-Spectrum clock ing. Output Features • 12 - 0.7V curr ent mode differential HCSL output pairs Features/Benefits • 3 Selectable SM Bus Addresses/Mulitple devices can shar e the same SMBus Segment • 12 OE# pin s/Hardware control of each output • P LL or bypass mode/PLL can dejitter inco ming clock • Selectable PLL bandwidth /minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/t racks spreading input clock for low EMI • SMBus Interface/unu.

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Twelve Output Differential Buffer for PCIe Gen3
DATASHEET
9DB1233
Recommended Application
12 output PCIe Gen3 zero-delay/fanout buffer
General Description
The 9DB1233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe Gen2
and Gen1. The 9DB1233 is driven by a differential SRC output
pair from an IDT 932S421 or 932SQ420 or equivalent main
clock generator. It attenuates jitter on the input clock and has a
selectable PLL bandwidth to maximize performance in systems
with or without Spread-Spectrum clocking.
Output Features
• 12 - 0.7V current mode differential HCSL output pairs
Features/Benefits
• 3 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 12 OE# pins/Hardware control of each output
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Supports undriven differential outputs in Power Down mode
for power management
Key Specifications
• Output cycle-cycle jitter < 50ps.
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• Pin compatible with DB1200 Yellow Cover Device
Functional Block Diagram
12
OE_(11:0)#
DIF_IN
DIF_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
12
DIF(11:0))
HIGH_BW#
BYPASS#/PLL
VTTPWRGD#/PD
ADR_SEL
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® Twelve Output Differential Buffer for PCIe Gen3
1
1675B—11/08/10

                    
                    






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