9DB233 Datasheet PDF Download, IDT





(PDF) 9DB233 Datasheet Download

Part Number 9DB233
Description Two Output Differential Buffer
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DB233 Datasheet PDF

Features: DATASHEET Two Output Differential Buffe r for PCIe Gen3 9DB233 Recommended Ap plication: 2 output PCIe Gen3 zero-dela y/fanout buffer General Description: Th e 9DB233 zero-delay buffer supports PCI e Gen3 requirements, while being backwa rds compatible to PCIe Gen2 and Gen1. T he 9DB233 is driven by a differential S RC output pair from an IDT 932S421 or 9 32SQ420 or equivalent main clock genera tor. It attenuates jitter on the input clock and has a selectable PLL bandwidt h to maximize performance in systems wi th or without Spread-Spectrum clocking. An SMBus interface allows control of t he PLL bandwidth and bypass options, wh ile 2 clock request (OE#) pins make the 9DB233 suitable for Express Card appli cations. Features/Benefits: • OE# pi ns/Suitable for Express Card applicatio ns • PLL or bypass mode/PLL can dejit ter incoming clock • Selectable PLL b andwidth/minimizes jitter peaking in do wnstream PLL's • Spread Spectrum Comp atible/tracks spreading input clock for low EMI • SMBus Inter.

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TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
DATASHEET
9DB233
Description
The 9DB233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB233 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator. It attenuates jitter on the
input clock and has a selectable PLL bandwidth to
maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows
control of the PLL bandwidth and bypass options, while 2
clock request (OE#) pins make the 9DB233 suitable for
Express Card applications.
Recommended Application
2 output PCIe Gen3 zero-delay/fanout buffer
Output Features
2 - 0.7V current mode differential HCSL output pairs
Features/Benefits
OE# pins; suitable for Express Card applications
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
SMBus Interface; allows control of PLL BW and Mode
Key Specifications
Cycle-to-cycle jitter < 50 ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
OE0#
OE1#
SRC_IN
SRC_IN#
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
DIF_0
DIF_1
IREF
IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
1
9DB233
OCTOBER 20, 2016

                    
                    






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