9DB833 Datasheet: EIGHT OUTPUT DIFFERENTIAL BUFFER





9DB833 EIGHT OUTPUT DIFFERENTIAL BUFFER Datasheet

Part Number 9DB833
Description EIGHT OUTPUT DIFFERENTIAL BUFFER
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9DB833 Datasheet PDF

Features: DATASHEET EIGHT OUTPUT DIFFERENTIAL BUF FER FOR PCIE GEN1,2,3 9DB833 General Description The 9DB833 zero-delay buffe r supports PCIe Gen3 requirements, whil e being backwards compatible to PCIe Ge n2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an ID T 932S421 or 932SQ420 or equivalent mai n clock generator. Recommended Applicat ion 8 output PCIe Gen1,2,3 zero-delay/f anout buffer Output Features • 8 - 0. 7V current-mode differential HCSL outpu t pairs • Supports zero delay buffer mode and fanout mode • Selectable ban dwidth • 50-110 MHz operation in PLL mode • 5-166 MHz operation in Bypass mode Features/Benefits • 3 Selectabl e SMBus Addresses; mulitple devices can share the same SMBus Segment • OE# p ins; suitable for Express Card applicat ions • PLL or bypass mode; PLL can de jitter incoming clock • Selectable PL L bandwidth; minimizes jitter peaking i n downstream PLL's • Spread Spectrum Compatible; tracks spreading input clock for low EMI • SMBus .

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DATASHEET
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
9DB833
General Description
The 9DB833 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB833 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Recommended Application
8 output PCIe Gen1,2,3 zero-delay/fanout buffer
Output Features
8 - 0.7V current-mode differential HCSL output pairs
Supports zero delay buffer mode and fanout mode
Selectable bandwidth
50-110 MHz operation in PLL mode
5-166 MHz operation in Bypass mode
Features/Benefits
3 Selectable SMBus Addresses; mulitple devices can
share the same SMBus Segment
OE# pins; suitable for Express Card applications
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
SMBus Interface; unused outputs can be disabled
Supports undriven differential outputs in Power Down
mode for power management
Key Specifications
Outputs cycle-cycle jitter <50ps
Output to Output skew <50ps
Phase jitter: PCIe Gen3 <1.0ps rm
Block Diagram
OE(7:0)#
8
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
STOP
LOGIC
8
DIF(7:0))
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
LOCK
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
1
9DB833
REV G 082515

                    
                    






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