9DBU0231 Data Sheet PDF | IDT





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Part Number 9DBU0231
Description 2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBU0231 Datasheet PDF

Features: 2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9DBU02 31 DATASHEET Description The 9DBU0231 is a member of IDT's 1.5V Ultra-Low-Po wer (ULP) PCIe family. The device has 2 output enables for clock management. R ecommended Application 1.5V PCIe Gen1-2 -3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 2 – 1-167MHz Low- Power (LP) HCSL DIF pairs Key Specifica tions • DIF cycle-to-cycle jitter <50 ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3 c ompliant • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF add itive phase jitter <350fs rms for 12k-2 0MHz Block Diagram Features/Benefits LP-HCSL outputs; save 4 resistors co mpared to standard HCSL outputs • 35m W typical power consumption in PLL mode ; eliminates thermal concerns • Sprea d Spectrum (SS) compatible; allows SS f or EMI reduction • OE# pins; support DIF power management • HCSL compatibl e differential input; can be driven by common clock sources • SMBus-selectable features; optimize si.

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9DBU0231 datasheet
2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0231
DATASHEET
Description
The 9DBU0231 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 2 output enables for clock
management.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
2 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <350fs rms for 12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs; save 4 resistors compared to standard
HCSL outputs
35mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF1
DIF0
9DBU0231 REVISION D 04/22/15 1 ©2015 Integrated Device Technology, Inc.

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