9DBU0431 Datasheet | 4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB





(Datasheet) 9DBU0431 Datasheet PDF Download

Part Number 9DBU0431
Description 4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9DBU0431 Datasheet PDF

Features: 4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9DBU04 31 DATASHEET Description The 9DBU0431 is a member of IDT's 1.5V Ultra-Low-Po wer (ULP) PCIe family. The device has 4 output enables for clock management, a nd 3 selectable SMBus addresses. Recomm ended Application 1.5V PCIe Gen1-2-3 Ze ro-Delay/Fan-out Buffer (ZDB/FOB) Outpu t Features • 4 – 1-167MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF cycle-to-cycle jitter <50ps DIF output-to-output skew <50ps • D IF phase jitter is PCIe Gen1-2-3 compli ant • DIF bypass mode additive phase jitter is <300fs rms for PCIe Gen3 • DIF bypass mode additive phase jitter < 350fs rms for 12k-20MHz Block Diagram Features/Benefits • LP-HCSL outputs; save 8 resistors compared to standard H CSL outputs • 45mW typical power cons umption in PLL mode; eliminates thermal concerns • Spread Spectrum (SS) comp atible; allows SS for EMI reduction • OE# pins; support DIF power management • HCSL-compatible differential input; can be driven by commo.

Keywords: 9DBU0431, datasheet, pdf, IDT, 4, O/P, 1.5V, PCIe, Gen1-2-3, ZDB/FOB, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0431
DATASHEET
Description
The 9DBU0431 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
HCSL outputs
45mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF3
DIF2
DIF1
DIF0
9DBU0431 REVISION C 04/22/15 1 ©2014 Integrated Device Technology, Inc.

                    
                    






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)