9DBU0531 Datasheet | 5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer





(PDF) 9DBU0531 pdf File Download

Part Number 9DBU0531
Description 5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBU0531 PDF File

Features: 5 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer 9DBU0531 DATASHEET Description The 9 DBU0531 is a member of IDT's 1.5V Ultra -Low-Power (ULP) PCIe family. The devic e has 5 output enables for clock manage ment, and 3 selectable SMBus addresses. Recommended Application 1.5V PCIe Gen1 -2-3 Fan-out Buffer (FOB) Output Featur es • 5 - 1-167MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF a dditive cycle-to-cycle jitter <5ps • DIF output-to-output skew <60ps • DIF additive phase jitter is <300fs rms fo r PCIe Gen3 • DIF additive phase jitt er <350s rms for SGMII Features/Benefi ts • LP-HCSL outputs; save 10 resisto rs compared to standard HCSL outputs 35mW typical power consumption; elimi nates thermal concerns • Spread Spect rum (SS) compatible; allows SS for EMI reduction • OE# pins for each output; support DIF power management • HCSL- compatible differential input; can be d riven by common clock sources • Sprea d Spectrum tolerant; allows reduction of EMI • SMBus-selectab.

Keywords: 9DBU0531, datasheet, pdf, IDT, 5-Output, 1.5V, PCIe, Gen1-2-3, Fanout, Buffer, , stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
9DBU0531
DATASHEET
Description
The 9DBU0531 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 5 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
5 1–167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter < 5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is < 300fs rms for PCIe Gen3
DIF additive phase jitter < 350fs rms for SGMII
Features/Benefits
LP-HCSL outputs; save 10 resistors compared to standard
HCSL outputs
35mW typical power consumption; eliminates thermal
concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
3.3V tolerant SMBus interface works with legacy controllers
3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
5 × 5 mm 32-VFQFPN; minimal board space
Block Diagram
vOE(4:0)#
5
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
,
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0531 MARCH 9, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
                    






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)