9DBU0731 Datasheet: 7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer





9DBU0731 7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer Datasheet

Part Number 9DBU0731
Description 7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBU0731 Datasheet PDF

Features: 7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer 9DBU0731 DATASHEET Description The 9 DBU0731 is a member of IDT's 1.5V Ultra -Low-Power (ULP) PCIe family. The devic e has 7 output enables for clock manage ment, and 3 selectable SMBus addresses. Recommended Application 1.5V PCIe Gen1 -2-3 Fan-out Buffer (FOB) Output Featur es • 7 – 1-167MHz Low-Power (LP) HC SL DIF pairs Key Specifications • DIF additive cycle-to-cycle jitter <5ps DIF output-to-output skew < 60ps • DIF additive phase jitter is <300fs rms for PCIe Gen3 • DIF additive phase j itter <350s rms for SGMII Block Diagra m vOE(6:0)# 7 CLK_IN CLK_IN# vSADR ^C KPWRGD_PD# SDATA_3.3 SCLK_3.3 CONTROL LOGIC Features/Benefits • LP-HCSL ou tputs; save 14 resistors compared to st andard HCSL outputs • 36mW typical po wer consumption; eliminates thermal con cerns • Outputs can optionally be sup plied from any voltage between 1.05 and 1.5V; maximum power savings • Spread Spectrum (SS) compatible; allows SS for EMI reduction • OE# .

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7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
9DBU0731
DATASHEET
Description
The 9DBU0731 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
7 – 1–167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter < 5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is < 300fs rms for PCIe Gen3
DIF additive phase jitter < 350s rms for SGMII
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
LP-HCSL outputs; save 14 resistors compared to standard
HCSL outputs
36mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
5 × 5 mm 40-VFQFPN package; minimal board space
` DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0731 MARCH 8, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
                    






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