9DBU0831 Datasheet: 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB





9DBU0831 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB Datasheet

Part Number 9DBU0831
Description 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBU0831 Datasheet PDF

Features: 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB 9DBU08 31 DATASHEET Description The 9DBU0831 is a member of IDT's 1.5V Ultra-Low-Po wer (ULP) PCIe family. The device has 8 output enables for clock management an d 3 selectable SMBus addresses. Recomme nded Application 1.5V PCIe Gen1-2-3 Zer o Delay/Fanout Buffer (ZDB/FOB) Output Features • 8 – 1-167MHz Low-Power ( LP) HCSL DIF pairs Key Specifications DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew < 75ps • DI F phase jitter is PCIe Gen1-2-3 complia nt • DIF bypass mode additive phase j itter is <300fs rms for PCIe Gen3 • D IF bypass mode additive phase jitter <3 50fs rms for 12k-20MHz Block Diagram F eatures/Benefits • LP-HCSL outputs; s ave 16 resistors compared to standard H CSL outputs • 53mW typical power cons umption in PLL mode; eliminates thermal concerns • Outputs can optionally be supplied from any voltage between 1.05 and 1.5V; maximum power savings • Sp read Spectrum (SS) compatible; allows SS for EMI reduction • .

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8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0831
DATASHEET
Description
The 9DBU0831 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 8 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
8 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 75ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs; save 16 resistors compared to standard
HCSL outputs
53mW typical power consumption in PLL mode; eliminates
thermal concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0831 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.

                    
                    






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