9DBU0841 Datasheet | 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB





(Datasheet) 9DBU0841 Datasheet PDF Download

Part Number 9DBU0841
Description 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBU0841 Datasheet PDF

Features: 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB w/Zo=10 0ohms 9DBU0841 DATASHEET Description The 9DBU0841 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It h as integrated output terminations provi ding Zo=100 for direct connection to 100 transmission lines. The device has 8 output enables for clock manageme nt and 3 selectable SMBus addresses. Re commended Application 1.5V PCIe Gen1-2- 3 Zero Delay/Fanout Buffer (ZDB/FOB) Ou tput Features • 8 – 1-167MHz Low-Po wer (LP) HCSL DIF pairs w/ZO=100 Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output s kew < 80ps • DIF phase jitter is PCIe Gen1-2-3 compliant • Very low additi ve phase jitter in bypass mode Block Di agram Features/Benefits • Direct con nection to 100 transmission lines; s aves 32 resistors compared to standard HCSL outputs • 53mW typical power con sumption in PLL mode; eliminates therma l concerns • Outputs can optionally b e supplied from any voltage between 1.05 and 1.5V; maximum powe.

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8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0841
DATASHEET
Description
The 9DBU0841 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100for direct connection to 100
transmission lines. The device has 8 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
8 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 80ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Very low additive phase jitter in bypass mode
Block Diagram
Features/Benefits
Direct connection to 100transmission lines; saves 32
resistors compared to standard HCSL outputs
53mW typical power consumption in PLL mode; eliminates
thermal concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0841 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.

                    
                    






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