9DBU0931 Datasheet | 9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer





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Part Number 9DBU0931
Description 9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
Manufacture IDT
Total Page 17 Pages
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Features: 9 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer 9DBU0931 DATASHEET Description The 9 DBU0931 is a member of IDT's 1.5V Ultra -Low-Power (ULP) PCIe family. The devic e has 9 output enables for clock manage ment, and 3 selectable SMBus addresses. Recommended Application 1.5V PCIe Gen1 -2-3 Fanout Buffer (FOB) Output Feature s • 9 – 1-167MHz Low-Power (LP) HCS L DIF pairs Key Specifications • DIF additive cycle-to-cycle jitter <5ps • DIF output-to-output skew < 60ps • D IF additive phase jitter is <300fs rms for PCIe Gen 3 • DIF additive phase j itter <350fs rms for SGMII Block Diagra m Features/Benefits • LP-HCSL output s; save 18 resistors compared to standa rd HCSL outputs • 47mW typical power consumption in PLL mode; minimal power consumption • Outputs can optionally be supplied from any voltage between 1. 05 and 1.5V; maximum power savings • Spread Spectrum (SS) compatible; allows SS for EMI reduction • OE# pins for each output; support DIF power management • HCSL-compatible d.

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9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
9DBU0931
DATASHEET
Description
The 9DBU0931 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
9 1–167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter < 5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is < 300fs rms for PCIe Gen 3
DIF additive phase jitter < 350fs rms for SGMII
Block Diagram
Features/Benefits
LP-HCSL outputs; save 18 resistors compared to standard
HCSL outputs
47mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
6 × 6 mm 48-VFQFPN; minimal board space
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0931 MARCH 9, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
                    






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