9DBU0941 Datasheet | 9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer





9DBU0941 PDF File (Datasheet) Download

Part Number 9DBU0941
Description 9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBU0941 PDF File

Features: 9 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer w/Zo=100ohms 9DBU0941 DATASHEET Descr iption The 9DBU0941 is a member of IDT' s 1.5V Ultra-Low-Power (ULP) PCIe famil y. It has integrated terminations for d irect connection to 100ohm transmission lines. The device has 9 output enables for clock management, and 3 selectable SMBus addresses. Recommended Applicati on 1.5V PCIe Gen1-2-3 Fanout Buffer (FO B) Output Features • 9 – 1-167MHz L ow-Power (LP) HCSL DIF pairs w/ZO=100 Key Specifications • DIF additive c ycle-to-cycle jitter <5ps • DIF outpu t-to-output skew < 60ps • DIF additiv e phase jitter is <300fs rms for PCIe G en3 • DIF additive phase jitter <350s rms for SGMII Block Diagram Features/ Benefits • Direct connection to 100oh m transmission lines; save 36 resistors compared to standard HCSL outputs • 47mW typical power consumption; elimina tes thermal concerns • Outputs can op tionally be supplied from any voltage b etween 1.05 and 1.5V; maximum power savings • Spread Spectrum.

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9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
with Zo=100ohms
9DBU0941
DATASHEET
Description
The 9DBU0941 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated terminations for direct
connection to 100transmission lines. The device has 9
output enables for clock management, and 3 selectable
SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
9 1–167MHz Low-Power (LP) HCSL DIF pairs with
ZO=100
Key Specifications
DIF additive cycle-to-cycle jitter < 5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is < 300fs rms for PCIe Gen3
DIF additive phase jitter < 350s rms for SGMII
Block Diagram
Features/Benefits
Direct connection to 100transmission lines; save 36
resistors compared to standard HCSL outputs
47mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
6 × 6 mm 48-VFQFPN; minimal board space
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0941 MARCH 9, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
                    






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