9DBV0241 Datasheet | 2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer





(Datasheet) 9DBV0241 Datasheet PDF Download

Part Number 9DBV0241
Description 2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBV0241 Datasheet PDF

Features: 2-Output 1.8V PCIe Gen1-2-3 Zero Delay / Fanout Buffer with Zo=100ohms 9DBV024 1 DATASHEET Description The 9DBV0241 i s a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 ou tput enables for clock management. Reco mmended Application 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Out put Features • 2 - 0.7V low-power HCS L-compatible (LP-HCSL) DIF pairs w/ZO=1 00 Key Specifications • DIF cycle- to-cycle jitter <50ps • DIF output-to -output skew <50ps • DIF additive pha se jitter is <100fs rms for PCIe Gen3 DIF additive phase jitter <300fs rms (12k-20MHz) Block Diagram Features/Be nefits • LP-HCSL outputs with Zo=100 ; saves 8 resistors compared to stand ard HCSL output • 35mW typical power consumption in PLL mode; minimal power consumption • Spread Spectrum (SS) co mpatible; allows use of SS for EMI redu ction • OE# pins; support DIF power m anagement • HCSL compatible different ial input; can be driven by common clock sources • SMBus-sele.

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2-Output 1.8V PCIe Gen1/2/3 Zero Delay /
Fanout Buffer with Zo=100ohms
9DBV0241
DATASHEET
Description
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 2 output enables for clock
management.
Recommended Application
1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
2 - 1-200MHz Low-Power (LP) HCSL DIF pairs w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms (12k-20MHz)
Block Diagram
Features/Benefits
LP-HCSL outputs with Zo=100; saves 8 resistors
compared to standard HCSL outputs
35mW typical power consumption in PLL mode; reduced
thermal concerns
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface; works with legacy
controllers
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBV0241 REVISION F 04/28/16 1 ©2016 Integrated Device Technology, Inc.

                    
                    






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